Voltage regulators, such as DC to DC converters, are used to provide stable voltage sources for electronic systems. Efficient DC to DC converters are particularly needed for battery management in low power devices, such as laptop notebooks and cellular phones. Switching voltage regulators (or simply “switching regulators”) are known to be an efficient type of DC to DC converter. A switching regulator generates an output voltage by converting an input DC voltage into a high frequency voltage, and filtering the high frequency input voltage to generate the output DC voltage. Specifically, the switching regulator includes a switch for alternately coupling and decoupling an input DC voltage source, such as a battery, to a load, such as an integrated circuit. An output filter, typically including an inductor and a capacitor, is coupled between the input voltage source and the load to filter the output of the switch and thus provide the output DC voltage. A controller, such as a pulse width modulator or a pulse frequency modulator, controls the switch to maintain a substantially constant output DC voltage.
LDMOS transistors are commonly used in switching regulators as a result of their performance in terms of a tradeoff between their specific on-resistance (Rdson) and drain-to-source breakdown voltage (BVd—s). Conventional LDMOS transistors are typically fabricated having optimized device performance characteristics through a complex process, such as a Bipolar-CMOS (BiCMOS) process or a Bipolar-CMOS-DMOS (BCD) process, that includes one or more process steps that are not compatible with sub-micron CMOS processes typically used by foundries specializing in production of large volumes of digital CMOS devices (e.g, 0.5 μm DRAM production technologies), as described in greater detail below. As a result, conventional LDMOS transistors are, therefore, not typically fabricated at such foundries.
A typical sub-micron CMOS process used by foundries specializing in production of large volumes of digital CMOS devices, referred to herein as sub-micron CMOS process, will now be described. A sub-micron CMOS process is generally used to fabricate sub-micron CMOS transistors—i.e., PMOS transistors and/or NMOS transistors having a channel length that is less than 1 μm. FIG. 1 shows a PMOS transistor 100 and an NMOS transistor 102 fabricated through a sub-micron CMOS process on a p-type substrate 104. The PMOS transistor 100 is implemented in a CMOS n-well 106. The PMOS transistor 100 includes a source region 108 and a drain region 110 having p-doped p+ regions 112 and 114, respectively. The PMOS transistor 100 further includes a gate 116 formed of a gate oxide 118 and a polysilicon layer 120. The NMOS transistor 102 is implemented in a CMOS p-well 122. The NMOS transistor 102 includes a source region 124 and a drain region 126 having n-doped n+ regions 128 and 130, respectively. The NMOS transistor 102 further includes a gate 132 formed of a gate oxide 134 and a polysilicon layer 136.
FIG. 2 illustrates a sub-micron CMOS process 200 that can be used to fabricate large volumes of sub-micron CMOS transistors (such as the CMOS transistors shown in FIG. 1). The process 200 begins with forming a substrate (step 202). The substrate can be a p-type substrate or an n-type substrate. Referring to FIG. 1, the CMOS transistors are fabricated on a p-type substrate 104. A CMOS n-well 106 for the PMOS transistor and a CMOS p-well 122 for the NMOS transistor are implanted into the substrate (step 204). The gate oxide 118, 134 of each CMOS transistor is formed, and a CMOS channel adjustment implant to control threshold voltages of each CMOS transistor is performed (step 206). A polysilicon layer 120, 136 is deposited over the gate oxide 118, 134, respectively (step 208). The p+ regions of the PMOS transistor and the n+ regions of the NMOS transistor are implanted (step 210). The p+ regions 112, 114 and n+ regions 128, 130 are highly doped, and provide low-resistivity ohmic contacts. In a sub-micron CMOS process, formation of an n+ region typically occurs through a three-step process in a single masking and photolithography step as follows: 1) a lightly doped n-type impurity region is implanted, 2) an oxide spacer is formed, and 3) a heavily doped n+ impurity region is implanted. Formation of a p+ region occurs in a similar manner. The formation such n+ and p+ regions allow transistors to have an improved hot carrier performance.
Foundries specializing in production of large volumes of digital CMOS devices generally have fixed parameters associated with the foundries' sub-micron CMOS process. These fixed parameters are typically optimized for the mass production of digital sub-micron CMOS transistors. For example, in process step 206, the CMOS channel adjustment implant generally has an associated thermal budget that is typically fixed, and has parameters optimized for mass production of sub-micron CMOS transistors.
As discussed above, conventional LDMOS transistors typically achieve optimized device performance through a complex process, such as a BiCMOS process or a BCD process, that includes one or more process steps that are not compatible with a sub-micron CMOS process optimized for the mass production of digital sub-micron CMOS transistors.
FIG. 3A shows a conventional LDMOS transistor 300 fabricated through a BiCMOS process on a p-type substrate 302. The LDMOS transistor 300 includes source region 304 with an n-doped n+ region 306, a p-doped p+ region 308, and a p-doped P-body diffusion (P-body) 310. The LDMOS transistor 300 also includes a drain region 312 with an n-doped n+ region 314 and an n-type well (HV n-well) 316, and a gate 318, including a gate oxide 320 and a polysilicon layer 322.
In the BiCMOS process, the gate oxide 320, and gate oxide of any CMOS transistors fabricated in the BiCMOS process, is formed prior to implantation of the n+ region 306 and the P-body 310. The BiCMOS process, therefore, allows the gate 318 to serve as a mask during implantation of the n+ region 306 and the P-body 310—i.e., the n+ region 306 and the P-body 310 are self aligned with respect to the gate 318. The self aligned lateral double diffusion of the n+ region 306 and the P-body 310 forms the channel of the LDMOS transistor 300.
Such kinds of self aligned double diffusions are not easily integrated into a sub-micron CMOS process because the subsequent drive-in step (or thermal budget) associated with self aligned double diffusions disrupts the fixed thermal budget associated with sub-micron CMOS process steps (e.g., process step 206) and requires a redesign of the thermal budget allocated to the sub-micron CMOS process steps. That is, the self aligned double diffusions generally includes a drive-in step with a long duration and a high temperature that can cause the characteristics of sub-micron CMOS transistors (e.g., threshold voltages) to shift.
The lateral doping profile in region (a) of the LDMOS transistor 300 controls the tradeoff between the on-resistance Rdson and the drain-to-source breakdown voltage BVd—s. The vertical doping profile in region (b) determines the drain-to-substrate breakdown voltage BVd—sub of the LDMOS transistor, and the pinch-off doping profile in region (c) determines the source-to-substrate punch-through breakdown voltage BVs—sub of the LDMOS transistor. The source-to-substrate punch-through breakdown voltage BVs—sub is an important parameter for an LDMOS transistor with a floating operation requirement, e.g, an LDMOS transistor implemented as a high-side control switch in a synchronous buck circuit configuration.
FIG. 3B shows a conventional LDMOS transistor 330 fabricated through a BCD process on a p-type substrate 332. The LDMOS transistor 330 includes source region 334 with an n-doped n+ region 336, a p-doped p+ region 338, and a p-doped P-body 340. The LDMOS transistor 330 also includes a drain region 342 with an n-doped n+ region 344 and an n-type layer (HV n-Epi) 346, and a gate 348, including a gate oxide 350 and a polysilicon layer 352. As with the BiCMOS process, in the BCD process, the gate oxide 350, and gate oxide of any CMOS transistors fabricated in the BCD process, is formed prior to implantation of the n+ region 336 and the P-body 340.
In the BCD process, an n+buried layer 354 can be grown on the p-type substrate 332 to improve the source-to-substrate punch-through breakdown characteristics of the LDMOS transistor. Such an approach offers an improved tradeoff between the on-resistance Rdson and drain-to-source breakdown voltage BVd—s of the LDMOS transistor as the lateral doping profile of the LDMOS transistor can be optimized without constrain on the vertical doping profiles. However, such a BCD process includes the growth of the HV n− Epi layer 346, and this step is generally not compatible with a sub-micron CMOS process.
Another approach used in a BCD process is to utilize an n− layer 360 implanted in the drain region 362 of the LDMOS transistor 364 as shown in FIG. 3C. The n− layer 360, n+ region 366, and P-body 368 are self aligned with respect to the gate 370—i.e., the n− layer 360, n+ region 366, and P-body 368 are implanted after formation of gate oxide 372. The inclusion of the n− layer 360 provides an additional parameter to further optimize the tradeoff between the on-resistance Rdson and drain-to-source breakdown voltage BVd—s of the LDMOS transistor. Similar to the n+ buried layer approach of FIG. 3B, the inclusion of the n− layer 360 at the surface provides a method to decouple vertical and horizontal doping constraints.